( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Computational memory-based inference and training of deep neural networks.

, , , , , , , , , , , , , , , и . VLSI Circuits, стр. 168-. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

S. R. Keshava

Ramya Nandakumar

Kannabiran Nandakumar

Murti von R S Devarakonda

Teresa S L R A Terreri

 

Другие публикации лиц с тем же именем

Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses., , , , , и . CoRR, (2019)Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators., , , , , , , , , и 3 other автор(ы). CoRR, (2023)Computational memory-based inference and training of deep neural networks., , , , , , , , , и 6 other автор(ы). VLSI Circuits, стр. 168-. IEEE, (2019)Live demonstration: Spiking neural circuit based navigation inspired by C. elegans thermotaxis., , , , , , и . ISCAS, стр. 1905. IEEE, (2015)Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation., , , , , , , , , и 21 other автор(ы). IRPS, стр. 1-6. IEEE, (2021)An efficient synaptic architecture for artificial neural networks., , , , , , , , и . NVMTS, стр. 1-4. IEEE, (2017)Deep learning acceleration based on in-memory computing., , , , , , , , , и 7 other автор(ы). IBM J. Res. Dev., 63 (6): 7:1-7:16 (2019)HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing., , , , , , , , , и 14 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2021)Phase-Change Memory Models for Deep Learning Training and Inference., , , , , , , и . ICECS, стр. 727-730. IEEE, (2019)Impact of conductance drift on multi-PCM synaptic architectures., , , , , , и . NVMTS, стр. 1-4. IEEE, (2018)