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Disambiguation of "Chih, Yu-Der"

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An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.

, , , , , , , , , , , , and . ISSCC, page 206-208. IEEE, (2011)

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Chih Chiu Yü

Yu-Chih Chiang

Yü Chih Chiu

Chih Chiu Yü

Matei Chihaia

 

Other publications of authors with the same name

An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices., , , , , , , , , and 4 other author(s). ISSCC, page 1-3. IEEE, (2022)29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification., , , , , and . ISSCC, page 404-406. IEEE, (2021)A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application., , , , and . A-SSCC, page 9-12. IEEE, (2017)A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications., , , , , , , , and . VLSI Technology and Circuits, page 24-25. IEEE, (2022)11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme., , , , and . ISSCC, page 200-201. IEEE, (2017)A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity., , , , , , , , , and 8 other author(s). ISSCC, page 494-495. IEEE, (2023)34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell., , , , , , , , , and 13 other author(s). ISSCC, page 572-574. IEEE, (2024)MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating., , , , , , , , , and 2 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2024)