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Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis.

, , , and . ITC, page 9. IEEE Computer Society, (2005)

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In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost., , , , , and . ITC, page 203-212. IEEE Computer Society, (2004)Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ., , , , , and . ITC, page 565-573. IEEE Computer Society, (2003)Impact of Multiple-Detect Test Patterns on Product Quality., , , , , , , and . ITC, page 1031-1040. IEEE Computer Society, (2003)A Hybrid Flow for Memory Failure Bitmap Classification., , , , , , and . Asian Test Symposium, page 314-319. IEEE Computer Society, (2012)Extracting Defect Density and Size Distributions from Product ICs., , , , , , , and . IEEE Des. Test Comput., 23 (5): 390-400 (2006)Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis., , , and . ITC, page 9. IEEE Computer Society, (2005)Minimum Testing Requirements to Screen Temperature Dependent Defects., , and . ITC, page 300-308. IEEE Computer Society, (2004)Achieving higher yield through diagnosis-the ASIC perspective.. ITC, page 2. IEEE Computer Society, (2005)Screening MinVDD Outliers Using Feed-Forward Voltage Testing., , , , , , , and . ITC, page 673-682. IEEE Computer Society, (2002)