( en | de | ru )

 

Disambiguation of "Stucchi, Michele"

Author of the publication

copydeleteadd this publication to your clipboard
Statistically Aware SRAM Memory Array Design.

, , , and . ISQED, page 25-30. IEEE Computer Society, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Michele Ocken

Michele Galletti

Michele Ferrari

Hannelore Michele

Michèle Mattusch

 

Other publications of authors with the same name

Design issues and considerations for low-cost 3D TSV IC technology., , , , , , , , , and 24 other author(s). ISSCC, page 148-149. IEEE, (2010)Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias., , , , , , , , , and 10 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2024)3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2009)Statistically Aware SRAM Memory Array Design., , , and . ISQED, page 25-30. IEEE Computer Society, (2006)Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions., , , , , , , , , and 8 other author(s). CICC, page 1-4. IEEE, (2010)Global interconnect trade-off for technology over memory modules to application level: case study., , , , , , , and . SLIP, page 125-132. ACM, (2003)Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node., , , , , , , , , and 4 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails., , , , , , , , , and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)Design Issues and Considerations for Low-Cost 3-D TSV IC Technology., , , , , , , , , and 27 other author(s). IEEE J. Solid State Circuits, 46 (1): 293-307 (2011)A tool flow for predicting system level timing failures due to interconnect reliability degradation., , , , , and . ACM Great Lakes Symposium on VLSI, page 291-296. ACM, (2008)