From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Design issues and considerations for low-cost 3D TSV IC technology., , , , , , , , , и 24 other автор(ы). ISSCC, стр. 148-149. IEEE, (2010)3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)., , , , , , , , , и 3 other автор(ы). 3DIC, стр. 1-5. IEEE, (2009)Statistically Aware SRAM Memory Array Design., , , и . ISQED, стр. 25-30. IEEE Computer Society, (2006)Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions., , , , , , , , , и 8 other автор(ы). CICC, стр. 1-4. IEEE, (2010)Global interconnect trade-off for technology over memory modules to application level: case study., , , , , , , и . SLIP, стр. 125-132. ACM, (2003)Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node., , , , , , , , , и 4 other автор(ы). VLSI Technology and Circuits, стр. 1-2. IEEE, (2023)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails., , , , , , , , , и 34 other автор(ы). VLSI Technology and Circuits, стр. 284-285. IEEE, (2022)Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits., , , , , и . ITC, стр. 1-10. IEEE, (2018)Impact of 3D design choices on manufacturing cost., , , , и . 3DIC, стр. 1-5. IEEE, (2009)A tool flow for predicting system level timing failures due to interconnect reliability degradation., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 291-296. ACM, (2008)