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Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited)., , , , , , , , , and 13 other author(s). ISCAS, page 1-5. IEEE, (2023)Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH)., , , , , , , , , and 12 other author(s). CF, page 191-193. ACM, (2021)A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing., , , , , , and . ISCAS, page 1-5. IEEE, (2024)Non-volatile memory as hardware synapse in neuromorphic computing: A first look at reliability issues., , , and . IRPS, page 6. IEEE, (2015)End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture., , , , , , and . DATE, page 1-6. IEEE, (2023)Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation., , , , , , , , , and 21 other author(s). IRPS, page 1-6. IEEE, (2021)An efficient synaptic architecture for artificial neural networks., , , , , , , , and . NVMTS, page 1-4. IEEE, (2017)ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator., , , , , , , , , and . IEEE Micro, 42 (6): 76-87 (2022)Accurate Weight Mapping in a Multi-Memristive Synaptic Unit., , , , , , , , , and . ISCAS, page 1-5. IEEE, (2021)Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited)., , , , , , , , , and 11 other author(s). IRPS, page 1-10. IEEE, (2023)