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Disambiguation of "Jiang, Hongwu"

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A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling.

, , , and . ESSCIRC, page 101-104. IEEE, (2022)

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Hongwu Zhang

Jiang Zhang

Jianzhong Jiang

Andong Jiang

Minhua Jiang

 

Other publications of authors with the same name

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training., , , , and . CoRR, (2020)A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling., , , and . ESSCIRC, page 101-104. IEEE, (2022)DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (11): 2306-2319 (2021)NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark., , , , and . Frontiers Artif. Intell., (2021)Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune., , and . NVMSA, page 1-6. IEEE, (2021)NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro., , , , and . AICAS, page 1-4. IEEE, (2021)Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine., , , and . MEMSYS, page 77-85. ACM, (2020)A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training., , , , , , , , , and . DAC, page 1-6. IEEE, (2020)Architecture and Circuit Design Optimization for Compute-In-Memory.. Georgia Institute of Technology, Atlanta, GA, USA, (2023)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/70137).A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays., , , and . VLSI Technology and Circuits, page 266-267. IEEE, (2022)