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Disambiguation of "Sato, Hideo"

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Comprehensive study on prediction of endurance properties from breakdown voltage in high-reliable STT-MRAM.

, , , , , , , , , , , , , , , , , , , and . IRPS, page 1-5. IEEE, (2023)

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Hideo Baba

Makoto Sato

Nobuko Sato

Fujio Sato

Hideo Ohashi

 

Other publications of authors with the same name

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz., , , , , , , , , and 6 other author(s). ISSCC, page 202-204. IEEE, (2019)Development of a finger-mounted tactile sensor for surface irregularity detection., , and . IROS, page 690-696. IEEE, (2007)Comprehensive study on prediction of endurance properties from breakdown voltage in high-reliable STT-MRAM., , , , , , , , , and 10 other author(s). IRPS, page 1-5. IEEE, (2023)A novel memory test system with an electromagnet for STT-MRAM testing., , , , , , and . NVMTS, page 1-4. IEEE, (2019)Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torque., , , , , and . ASP-DAC, page 684-691. IEEE, (2014)Personalizing the Appearance of Content Packages., and . LWA, page 42-47. Humbold-Universität Berlin, (2004)Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure., , , , , , , , , and 1 other author(s). VLSIC, page 172-. IEEE, (2015)Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Real-time inspection of surface irregularity by finger-mounted tactile sensor., , and . RO-MAN, page 442-447. IEEE, (2009)