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A 32nm 0.5V-supply dual-read 6T SRAM., , , , , , , , , и 5 other автор(ы). CICC, стр. 1-4. IEEE, (2010)Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor., , , , , , , , , и 7 other автор(ы). CICC, стр. 235-238. IEEE, (2005)SRAM device and cell co-design considerations in a 14nm SOI FinFET technology., , , , , , , и . ISCAS, стр. 2339-2342. IEEE, (2013)A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS., , , , , , , , , и 11 other автор(ы). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)A low latency and low power dynamic Carry Save Adder., , , , , , , и . ISCAS (2), стр. 477-480. IEEE, (2004)Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability., , , , , , и . ESSDERC, стр. 234-237. IEEE, (2013)SRAM bitline circuits on PD SOI: advantages and concerns., , , , , , , и . IEEE J. Solid State Circuits, 32 (6): 837-844 (1997)SRAM Local Bit Line Access Failure Analyses., , , , , и . ISQED, стр. 204-209. IEEE Computer Society, (2006)Statistical yield analysis of silicon-on-insulator embedded DRAM., , , , , , , и . ISQED, стр. 190-194. IEEE Computer Society, (2009)Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs., , , , , , , и . ISQED, стр. 33-40. IEEE Computer Society, (2007)