( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A New Colum Redundancy Scheme For Fast Access Time of 64-Mb DRAM.

, , , , , , , , и . ISCAS, стр. 1937-1940. IEEE, (1993)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Seong-Jin Choi

Kuk Jin Jang

Seong Jin Choi

Ki-Chang Seong

Seunghyeon Seong

 

Другие публикации лиц с тем же именем

An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM., , , , , , , , , и 7 other автор(ы). A-SSCC, стр. 139-142. IEEE, (2018)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process., , , , , , , , , и 16 other автор(ы). VLSI Circuits, стр. 147-148. IEEE, (2018)A Study on Knocking Analysis Simulator Based on CRDI Engine ECU., , и . FGIT-GDC/IESH/CGAG, том 351 из Communications in Computer and Information Science, стр. 255-262. Springer, (2012)18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 314-315. IEEE, (2016)A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques., , , , , , , , , и 16 other автор(ы). ISSCC, стр. 278-279. IEEE, (2008)23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS., , , , , , , , и . ISSCC, стр. 400-401. IEEE, (2017)An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion., , , , , , , , , и 19 other автор(ы). ISSCC, стр. 492-617. IEEE, (2007)A Study on Dynamic Gateway System for MOST GATEWAY Scheduling Algorithm in MOST25 and MOST150 Networks., и . ICHIT (1), том 6935 из Lecture Notes in Computer Science, стр. 45-53. Springer, (2011)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM., , , , , , и . DAC, стр. 91:1-91:6. ACM, (2015)A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface., , , , , , , , и . IEEE J. Solid State Circuits, 53 (1): 144-154 (2018)