( en | de | ru )

 

Disambiguation of "Sato, Yasuo"

Author of the publication

copydeleteadd this publication to your clipboard
Good Die Prediction Modelling from Limited Test Items.

, , , and . ITC-Asia, page 115-120. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yasuo Kamata

Yasuo Tokunaga

Makoto Sato

Yasuo Nakayama

Nobuko Sato

 

Other publications of authors with the same name

Scan-Out Power Reduction for Logic BIST., , , and . IEICE Trans. Inf. Syst., 96-D (9): 2012-2020 (2013)On-Chip Delay Measurement for In-Field Test of FPGAs., , and . PRDC, page 130-137. IEEE, (2019)Not all Delay Tests Are the Same - SDQL Model Shows True-Time., , , , , and . ATS, page 147-152. IEEE, (2006)Good Die Prediction Modelling from Limited Test Items., , , and . ITC-Asia, page 115-120. IEEE, (2018)An evaluation of defect-oriented test: WELL-controlled low voltage test., , , , and . ITC, page 1059-1067. IEEE Computer Society, (2001)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , and . Asian Test Symposium, page 19-24. IEEE Computer Society, (2013)An On-Chip Digital Environment Monitor for Field Test., , , and . ATS, page 254-257. IEEE Computer Society, (2014)A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST., , , , and . ATS, page 203-208. IEEE Computer Society, (2016)An Approach to Improve the Resolution of Defect-Based Diagnosis., , , , and . Asian Test Symposium, page 123-. IEEE Computer Society, (2001)Effective Post-BIST Fault Diagnosis for Multiple Faults., , , , , , and . DFT, page 401-109. IEEE Computer Society, (2006)