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Другие публикации лиц с тем же именем

On the fault diagnosis in the presence of unknown fault models using pass/fail information., , , , и . ISCAS (3), стр. 2987-2990. IEEE, (2005)Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits., , , , и . ASP-DAC, стр. 659-664. IEEE, (2006)Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors., , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (12): 3506-3513 (2008)On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects., , , , и . ISCIT, стр. 1-5. IEEE, (2017)Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines., , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2842-2850 (2017)Test cost reduction for logic circuits: Reduction of test data volume and test application time., , , и . Syst. Comput. Jpn., 36 (6): 69-83 (2005)Comparative Evaluation of Bluetooth and Wi-Fi Direct for Tablet-Oriented Educational Applications., , , , и . ACIIDS (1), том 10191 из Lecture Notes in Computer Science, стр. 345-354. (2017)Formulation of a Test Pattern Measure That Counts Distinguished Fault-Pairs for Circuit Fault Diagnosis., и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (12): 1456-1463 (2020)Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique., , и . Asian Test Symposium, стр. 94-99. IEEE Computer Society, (1996)On Detecting Transition Faults in the Presence of Clock Delay Faults., , , и . Asian Test Symposium, стр. 1-6. IEEE Computer Society, (2011)