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CMOS SRAM scaling limits under optimum stability constraints.

A. Makosiej, O. Thomas, A. Amara, and A. Vladimirescu. ISCAS, page 1460-1463. IEEE, (2013)

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Adam Gruber

Jost Adam

Marion Adam

Adam Pluskota

Adam Williamson

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Tunnel FET based ultra-low-leakage compact 2T1C SRAM.N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, and C. Anghel. ISQED, page 71-75. IEEE, (2017)Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications.N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, and C. Anghel. ISQED, page 107-112. IEEE, (2016)3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications.N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, and C. Anghel. DATE, page 361-366. IEEE, (2016)SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch.P. Nasalski, A. Makosiej, B. Giraud, A. Vladimirescu, and A. Amara. ISCAS, page 3170-3173. IEEE, (2009)CMOS SRAM scaling limits under optimum stability constraints.A. Makosiej, O. Thomas, A. Amara, and A. Vladimirescu. ISCAS, page 1460-1463. IEEE, (2013)SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency.I. Panades, B. Tain, J. Christmann, D. Coriat, R. Lemaire, C. Jany, B. Martineau, F. Chaix, A. Quelen, E. Pluchart and 11 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes.A. Vladimirescu, C. Anghel, A. Amara, N. Gupta, and A. Makosiej. IWASI, page 266-270. IEEE, (2015)TFET NDR skewed inverter based sensing method.N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, S. Cotofana, and C. Anghel. NANOARCH, page 13-14. ACM, (2016)Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.R. Boumchedda, J. Noel, B. Giraud, A. Makosiej, M. Rios, E. Esmanhotto, E. Bourde-Cicé, M. Bellet, D. Turgis, and E. Beigné. NANOARCH, page 131-137. ACM, (2018)16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell.N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, and C. Anghel. ESSDERC, page 356-359. IEEE, (2016)

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Disambiguation of "Makosiej, Adam"

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CMOS SRAM scaling limits under optimum stability constraints.

Please choose a person to relate this publication to

Adam Gruber

Jost Adam

Marion Adam

Adam Pluskota

Adam Williamson

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Makosiej, Adam"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML CMOS SRAM scaling limits under optimum stability constraints.

Please choose a person to relate this publication to

Adam Gruber

Jost Adam

Marion Adam

Adam Pluskota

Adam Williamson

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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CMOS SRAM scaling limits under optimum stability constraints.