( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
CMOS SRAM scaling limits under optimum stability constraints.

, , , и . ISCAS, стр. 1460-1463. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Adam Bär

Adam Zomotor

Olaf Adam

Karlheinz Adam

Elke Adam

 

Другие публикации лиц с тем же именем

CMOS SRAM scaling limits under optimum stability constraints., , , и . ISCAS, стр. 1460-1463. IEEE, (2013)SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch., , , , и . ISCAS, стр. 3170-3173. IEEE, (2009)SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency., , , , , , , , , и 11 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2020)TFET NDR skewed inverter based sensing method., , , , , и . NANOARCH, стр. 13-14. ACM, (2016)Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes., , , , и . IWASI, стр. 266-270. IEEE, (2015)Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology., , , , , , , , , и . NANOARCH, стр. 131-137. ACM, (2018)16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell., , , , и . ESSDERC, стр. 356-359. IEEE, (2016)1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell., , , , и . ESSCIRC, стр. 316-319. IEEE, (2017)An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch., , , , и . ICECS, стр. 554-557. IEEE, (2008)Tunnel FET based ultra-low-leakage compact 2T1C SRAM., , , , и . ISQED, стр. 71-75. IEEE, (2017)