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Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM., , , , , , , , , and 25 other author(s). A-SSCC, page 153-156. IEEE, (2017)17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM., , , , , , , , , and 7 other author(s). A-SSCC, page 139-142. IEEE, (2018)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process., , , , , , , , , and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs., , , , , , , , , and 1 other author(s). VLSIC, page 1-2. IEEE, (2014)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme., , , , , , , , , and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)., , , , , , , , , and 9 other author(s). A-SSCC, page 169-172. IEEE, (2016)