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A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters.

, , , , , , , , и . NEWCAS, стр. 20-24. IEEE, (2022)

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Simone Marion

Ernst Marioth-Wirtz

Martin Marioth

Anneliese Marioth

Ilias Mariolakos

 

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A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity., , , и . ICECS, стр. 1-4. IEEE, (2021)A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters., , , , , , , , и . NEWCAS, стр. 20-24. IEEE, (2022)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 456-458. IEEE, (2021)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 445-447. IEEE, (2021)Techniques for low-jitter and low-area occupation fractional-N Frequency synthesis.. Polytechnic University of Milan, Italy, (2020)A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter., , , и . A-SSCC, стр. 1-3. IEEE, (2021)Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (5): 1858-1870 (2022)A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power., , , , и . CICC, стр. 1-4. IEEE, (2019)17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking., , , , , , , и . ISSCC, стр. 268-270. IEEE, (2020)17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter., , , , , , , и . ISSCC, стр. 274-276. IEEE, (2020)