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Disambiguation of "Fukami, Shunsuke"

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Double Free-Layer Magnetic Tunnel Junctions for Probabilistic Bits.

, , , , and . CoRR, (2020)

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Shunsuke Saito

 

Other publications of authors with the same name

A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms., , , , , , , , , and 2 other author(s). CoRR, (2023)Double-Free-Layer Stochastic Magnetic Tunnel Junctions with Synthetic Antiferromagnets., , , , , and . CoRR, (2023)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications., , , , , , , , , and 4 other author(s). ISSCC, page 184-185. IEEE, (2014)Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Double Free-Layer Magnetic Tunnel Junctions for Probabilistic Bits., , , , and . CoRR, (2020)A 90nm 12ns 32Mb 2T1MTJ MRAM., , , , , , , , , and 10 other author(s). ISSCC, page 462-463. IEEE, (2009)Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torque., , , , , and . ASP-DAC, page 684-691. IEEE, (2014)Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure., , , , , , , , , and 1 other author(s). VLSIC, page 172-. IEEE, (2015)High-speed simulator including accurate MTJ models for spintronics integrated circuit design., , , , , , , , , and 1 other author(s). ISCAS, page 1971-1974. IEEE, (2012)