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Disambiguation of "Noel, Jean-Philippe"

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Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution.

, , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 40:1-40:26 (2022)

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Jean-Noël Quintin

Jean-Noel Marsat

Jean-Noël Martin

Jean-Philippe Dubus

Jean-Philippe Kohl

 

Other publications of authors with the same name

An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper., , , , , , , and . SLIP, page 4:1-4:7. ACM, (2022)Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (12): 2599-2607 (2018)Binary ReRAM-based BNN first-layer implementation., , , , , , , , and . DATE, page 1-6. IEEE, (2023)Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges., , , , , , , and . ESSCIRC, page 83-86. IEEE, (2021)Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology., , , , , , and . VLSI-SoC, page 168-173. IEEE, (2013)Reliable ReRAM-based Logic Operations for Computing in Memory., , , , , , and . VLSI-SoC, page 192-195. IEEE, (2018)Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop., , , , , , and . ISCAS, page 1-4. IEEE, (2017)Architecture, design and technology guidelines for crosspoint memories., , , , , and . NANOARCH, page 55-60. IEEE, (2017)Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology., , , , , , , , , and . NANOARCH, page 131-137. ACM, (2018)A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures., , , , and . DATE, page 1-6. IEEE, (2024)