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On Using Implied Values in EDT-based Test Compression., , , , and . DAC, page 11:1-11:6. ACM, (2014)Built-In Self-Test for Systems on Silicon., , and . VLSI Design, page 609-610. IEEE Computer Society, (1999)Embedded deterministic test points for compact cell-aware tests., , , , , , , , , and . ITC, page 1-8. IEEE, (2015)Self-test methodology for at-speed test of crosstalk in chip interconnects., , and . DAC, page 619-624. ACM, (2000)Hybrid Ring Generators for In-System Test Applications., , , and . ETS, page 1-6. IEEE, (2023)Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects., , , , , , , , , and . ATS, page 139-146. IEEE, (2006)Test Generation for an Iterative Design Flow with RTL Changes., , , and . ITC, page 305-313. IEEE, (2022)DIST: Deterministic In-System Test with X-masking., , , and . ITC, page 20-27. IEEE, (2022)Diagnosis with Limited Failure Information., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits., and . ITC, page 473-482. IEEE Computer Society, (1991)