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Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs.

, and . DATE, page 490-494. IEEE Computer Society, (1998)

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Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability., and . EDAC-ETC-EUROASIC, page 356-360. IEEE Computer Society, (1994)Gate Leakage Impact on Full Open Defects in Interconnect Lines., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2209-2220 (2011)Bridging Defects Resistance Measurements in a CMOS Process., , and . ITC, page 892-899. IEEE Computer Society, (1992)Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs., and . DATE, page 490-494. IEEE Computer Society, (1998)Post-bond test of Through-Silicon Vias with open defects., , and . ETS, page 1-6. IEEE, (2014)Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1739-1748 (2016)Quiescent current analysis and experimentation of defective CMOS circuits., , , , and . J. Electron. Test., 3 (4): 337-348 (1992)Power-aware voltage tuning for STT-MRAM reliability., , , , , , and . ETS, page 1-6. IEEE, (2015)Diagnosis of full open defects in interconnect lines with fan-out., , , , , and . European Test Symposium, page 233-238. IEEE Computer Society, (2010)Delay caused by resistive opens in interconnecting lines., , and . Integr., 42 (3): 286-293 (2009)