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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.

, , , , , , , , , , , , , , , , , , , , и . ISSCC, стр. 250-252. IEEE, (2021)

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Chi-Chou Yeh

Chi-Wu Chou

Yen Yen Kwan

Tina Yener

Nazlı Yener Aǧabeyoǧlu

 

Другие публикации лиц с тем же именем

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips., , , , , , , , , и 15 other автор(ы). IEEE J. Solid State Circuits, 57 (2): 609-624 (2022)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips., , , , , , , , , и 13 other автор(ы). ISSCC, стр. 240-242. IEEE, (2020)A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training., , , , , , , , , и . DAC, стр. 1-6. IEEE, (2020)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips., , , , , , , , , и 11 other автор(ы). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (апреля 2024)A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips., , , , , , , , , и 15 other автор(ы). IEEE J. Solid State Circuits, 58 (3): 877-892 (марта 2023)A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips., , , , , , , , , и 11 other автор(ы). IEEE J. Solid State Circuits, 56 (9): 2817-2831 (2021)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips., , , , , , , , , и 17 other автор(ы). ISSCC, стр. 246-248. IEEE, (2020)16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips., , , , , , , , , и 11 other автор(ы). ISSCC, стр. 250-252. IEEE, (2021)