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BIST Technique by Equally Spaced Test Vector Sequences.

, , , , , , и . VTS, стр. 206-216. IEEE Computer Society, (2004)

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Daniel Rodríguez

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Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability., и . EDAC-ETC-EUROASIC, стр. 356-360. IEEE Computer Society, (1994)Gate Leakage Impact on Full Open Defects in Interconnect Lines., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2209-2220 (2011)Bridging Defects Resistance Measurements in a CMOS Process., , и . ITC, стр. 892-899. IEEE Computer Society, (1992)Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs., и . DATE, стр. 490-494. IEEE Computer Society, (1998)Post-bond test of Through-Silicon Vias with open defects., , и . ETS, стр. 1-6. IEEE, (2014)Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents., , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1739-1748 (2016)Quiescent current analysis and experimentation of defective CMOS circuits., , , , и . J. Electron. Test., 3 (4): 337-348 (1992)Power-aware voltage tuning for STT-MRAM reliability., , , , , , и . ETS, стр. 1-6. IEEE, (2015)Delay caused by resistive opens in interconnecting lines., , и . Integr., 42 (3): 286-293 (2009)Diagnosis of full open defects in interconnect lines with fan-out., , , , , и . European Test Symposium, стр. 233-238. IEEE Computer Society, (2010)