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Disambiguation of "Chattopadhyay, Santanu"

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KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (3): 257-265 (1997)

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Anupam Chattopadhyay

Santanu Sarma

Santanu Mukherjee

Dhrupadi Chattopadhyay

Santanu Pal

 

Other publications of authors with the same name

Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption., , and . IEEE Trans. Emerg. Top. Comput., 9 (4): 2109-2124 (2021)Low power finite state machine synthesis using power-gating., , and . Integr., 44 (3): 175-184 (2011)Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach., , , , , and . ICIT, page 228-233. IEEE, (2019)Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure., , and . ISCAS, page 1-5. IEEE, (2019)Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing., , and . Integr., 45 (2): 211-221 (2012)Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling., and . Integr., (2015)Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution., , and . Integr., (2018)Reliability-aware application mapping onto mesh based Network-on-Chip., , and . Integr., (2018)Confidence Based Power Aware Testing., , , and . ISED, page 62-66. IEEE, (2012)Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization., , and . ISED, page 172-176. IEEE, (2012)