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A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating., , , , , , , , , and 4 other author(s). ISSCC, page 194-195. IEEE, (2013)A 90nm 12ns 32Mb 2T1MTJ MRAM., , , , , , , , , and 10 other author(s). ISSCC, page 462-463. IEEE, (2009)Soft-Delay-Error Evaluation in Content-Addressable Memory., , , , , and . ISMVL, page 220-225. IEEE Computer Society, (2014)High-speed simulator including accurate MTJ models for spintronics integrated circuit design., , , , , , , , , and 1 other author(s). ISCAS, page 1971-1974. IEEE, (2012)28nm Atom-Switch FPGA: Static Timing Analysis and Evaluation., , , , , , , , , and 1 other author(s). IEICE Trans. Electron., 105-C (10): 627-630 (October 2022)A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)ON-state retention of Atom Switch eNVM for IoT/AI Inference Solution., , , , , , , , , and 2 other author(s). IRPS, page 1-4. IEEE, (2020)Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs., , , and . CICC, page 355-358. IEEE, (2008)Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 57 (7): 2250-2262 (2022)