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Disambiguation of "Chen, Yen-Huei"

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A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications.

, , , , , , , and . A-SSCC, page 185-188. IEEE, (2016)

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Yen-Huei Chen

Huei-Ling Yen

Guo-Huei Chen

Jyh-Huei Chen

Huei-Mei Chen

 

Other publications of authors with the same name

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications., , , , , , , , , and 5 other author(s). ISSCC, page 316-317. IEEE, (2013)A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 50 (1): 170-177 (2015)A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 4nm 6163-TOPS/W/b $4790-TOPS/mm^2/b$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update., , , , , , , , , and 8 other author(s). ISSCC, page 132-133. IEEE, (2023)A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue., , , , , , , , , and . ISSCC, page 390-392. IEEE, (2019)15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications., , , , , , , , , and 2 other author(s). ISSCC, page 238-240. IEEE, (2020)An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications., , , , , , , , , and 10 other author(s). ISSCC, page 252-254. IEEE, (2021)A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue., , , , , , , , , and . ISSCC, page 340-342. IEEE, (2021)A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications., , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)