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A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme., , , , , , , , , и 8 other автор(ы). IEEE J. Solid State Circuits, 33 (11): 1772-1780 (1998)Improvement of Factor Model with Text Information Based on Factor Model Construction Process., , , и . IIMSS, том 254 из Frontiers in Artificial Intelligence and Applications, стр. 222-230. IOS Press, (2013)MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing., и . ISCA, стр. 443-451. IEEE Computer Society, (1988)A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI., , , , , , , , , и 1 other автор(ы). CICC, стр. 527-530. IEEE, (2005)Substrate noise influence on circuit performance in variable threshold-voltage scheme., , , , , , и . ISLPED, стр. 309-312. IEEE, (1996)A single-chip 802.11a MAC/PHY with a 32-b RISC processor., , , , , , и . IEEE J. Solid State Circuits, 38 (11): 2001-2009 (2003)A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme., , , , , , , , , и 3 other автор(ы). IEEE J. Solid State Circuits, 31 (11): 1770-1779 (1996)A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 326-327. IEEE, (2010)Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 14 (12): 1379-1383 (2006)A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS., , , и . ISSCC, стр. 338-340. IEEE, (2011)