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Disambiguation of "Honjo, Hiroaki"

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MRAM Cell Technology for Over 500-MHz SoC.

, , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 830-838 (2007)

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Hiroaki Kobayashi

Hiroaki Tanaka

 

Other publications of authors with the same name

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications., , , , , , , , , and 4 other author(s). ISSCC, page 184-185. IEEE, (2014)Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 90nm 12ns 32Mb 2T1MTJ MRAM., , , , , , , , , and 10 other author(s). ISSCC, page 462-463. IEEE, (2009)1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times., , , , , , , , and . VLSIC, page 46-47. IEEE, (2012)Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure., , , , , , , , , and 1 other author(s). VLSIC, page 172-. IEEE, (2015)High-speed simulator including accurate MTJ models for spintronics integrated circuit design., , , , , , , , , and 1 other author(s). ISCAS, page 1971-1974. IEEE, (2012)MRAM Cell Technology for Over 500-MHz SoC., , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 830-838 (2007)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz., , , , , , , , , and 6 other author(s). ISSCC, page 202-204. IEEE, (2019)Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating., , , , , , , , , and 4 other author(s). ISSCC, page 194-195. IEEE, (2013)