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Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor.

T. Beacom, T. Buchholtz, D. Bradley, J. Randolph, S. Storino, M. Veldhuizen, S. Dance, J. Kuang, S. Schwinn, S. Cox, F. Ziegler, J. Kao, C. Li, C. Tretz, J. Cabellon, A. Freemyer, and M. Tubbs. CICC, page 235-238. IEEE, (2005)

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Jente Brünjes

Pei Kuang

Alfred Jenter

Walter Christian Jenter

Matthias Jenter

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Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor.T. Beacom, T. Buchholtz, D. Bradley, J. Randolph, S. Storino, M. Veldhuizen, S. Dance, J. Kuang, S. Schwinn, S. Cox and 7 other author(s). CICC, page 235-238. IEEE, (2005)A 32nm 0.5V-supply dual-read 6T SRAM.J. Kuang, J. Schaub, F. Gebara, D. Wendel, S. Saroop, T. Nguyen, T. Fröhnel, A. Müller, C. Durham, R. Sautter and 5 other author(s). CICC, page 1-4. IEEE, (2010)SRAM device and cell co-design considerations in a 14nm SOI FinFET technology.B. Cheng, X. Wang, A. Brown, J. Kuang, D. Reid, C. Millar, S. Nassif, and A. Asenov. ISCAS, page 2339-2342. IEEE, (2013)A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.P. Klim, J. Barth, W. Reohr, D. Dick, G. Fredeman, G. Koch, H. Le, A. Khargonekar, P. Wilcox, J. Golz and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)A low latency and low power dynamic Carry Save Adder.R. Datta, J. Abraham, R. Montoye, W. Belluomini, H. Ngo, C. McDowell, J. Kuang, and K. Nowka. ISCAS (2), page 477-480. IEEE, (2004)Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability.X. Wang, B. Cheng, A. Brown, C. Millar, J. Kuang, S. Nassif, and A. Asenov. ESSDERC, page 234-237. IEEE, (2013)SRAM bitline circuits on PD SOI: advantages and concerns.J. Kuang, S. Ratanaphanyarat, M. Saccamango, L. Hsu, R. Flaker, L. Wagner, S. Chu, and G. Shahidi. IEEE J. Solid State Circuits, 32 (6): 837-844 (1997)SRAM Local Bit Line Access Failure Analyses.P. Elakkumanan, J. Kuang, K. Nowka, R. Sridhar, R. Kanj, and S. Nassif. ISQED, page 204-209. IEEE Computer Society, (2006)Statistical yield analysis of silicon-on-insulator embedded DRAM.R. Kanj, R. Joshi, J. Kuang, J. Kim, M. Meterelliyoz, W. Reohr, S. Nassif, and K. Nowka. ISQED, page 190-194. IEEE Computer Society, (2009)Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.R. Kanj, R. Joshi, J. Sivagnaname, J. Kuang, D. Acharyya, T. Nguyen, C. McDowell, and S. Nassif. ISQED, page 33-40. IEEE Computer Society, (2007)

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Disambiguation of "Kuang, Jente B."

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Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor.

Please choose a person to relate this publication to

Jente Brünjes

Pei Kuang

Alfred Jenter

Walter Christian Jenter

Matthias Jenter

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kuang, Jente B."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor.

Please choose a person to relate this publication to

Jente Brünjes

Pei Kuang

Alfred Jenter

Walter Christian Jenter

Matthias Jenter

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor.