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Improving LUT-based optimization for ASICs., , , , , , и . DAC, стр. 421-426. ACM, (2022)Transistor Count Optimization in IG FinFET Network Design., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)Efficient transistor-level design of CMOS gates., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 191-196. ACM, (2013)Graph-Based Transistor Network Generation Method for Supergate Design., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 692-705 (2016)Performance evaluation of optimized transistor networks built using independent-gate FinFET., , , , и . LASCAS, стр. 227-230. IEEE, (2016)Exact Benchmark Circuits for Logic Synthesis., , , , , , и . IEEE Des. Test, 37 (3): 51-58 (2020)SAT-Sweeping Enhanced for Logic Synthesis., , , , , , , , и . DAC, стр. 1-6. IEEE, (2020)Unlocking fine-grain parallelism for AIG rewriting., , , , , и . ICCAD, стр. 87. ACM, (2018)NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements., , , , , и . SBCCI, стр. 1-6. IEEE, (2012)Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation., , , , , и . SBCCI, стр. 1-6. IEEE, (2018)